This relates to pulse width modulation methods for image display systems, especially suitable for application to loading spatial light modulators with image data.
Many modern image display systems utilize spatial light modulators (SLMs). SLMs comprise arrays of individually addressable and controllable pixel elements that modulate light according to input data streams corresponding to image frame pixel data.
Digital micromirror devices (DMDs) are a type of SLM, and may be used for either direct-view or projection display applications. A DMD has an array of micromechanical pixel elements, each having a tiny mirror that is individually addressable by an electronic signal. Depending on the state of its addressing signal, each mirror element tilts so that it either does or does not reflect light to the image plane. Other SLMs operate on similar principles, with arrays of pixel elements that may emit or reflect light simultaneously with other pixel elements, such that a complete image is generated by sequences of addressing the pixel elements. Another example of an SLM is a liquid crystal display (LCD) which has individually driven pixel elements. Typically, displaying each frame of pixel data is accomplished by loading memory cells so that pixel elements can be simultaneously addressed.
In a typical SLM display system, pulse-width modulation (PWM) techniques are used to achieve intermediate levels of illumination, between white (ON) and black (OFF), corresponding to gray levels of intensity. A basic PWM scheme involves first determining a rate at which images are to be presented to a viewer. This establishes a frame rate and a corresponding frame period. For example, in a standard television system, images may be transmitted at 30 frames per second, and each frame lasts for approximately 33.3 milliseconds. Then, an intensity resolution for each pixel element is established. For example, to achieve an intensity resolution of n bits per frame, the frame time may be divided into 2n-1 equal time slices. Thus, for a 33.3 millisecond frame period and n-bit intensity values, each time slice has a duration of 33.3/2n-1 milliseconds.
Once the desired resolution (number of intensity bits per pixel per frame) and time slice duration (milliseconds per time slice) are determined, pixel intensities are quantized for each pixel of each frame with a least significant bit (LSB) corresponding to one time slice. For example, black having minimum intensity with illumination for zero time slices may be represented with all bits=0, and white having maximum intensity with illumination for all time slices (2n-1 time slices) may be represented with all bits=1. Each pixel's quantized intensity determines its on-time during a frame period. Thus, during a frame period, each pixel with a quantized value of more than 0 is ON for the number of time slices that correspond to its intensity. The viewer's eye integrates the pixel brightness so that the image appears the same as if it were generated with analog levels of light.
For addressing SLMs, PWM calls for the data to be formatted into “bit-planes,” each bit-plane corresponding to a bit weight of the intensity value. Thus, if intensity is represented by an n-bit value, each frame of data has n bit-planes. Each bit-plane has a 0 or 1 value for each pixel element. In the basic PWM scheme described above, during a frame, each of the n bit-planes is separately loaded and the pixel elements addressed according to their respective associated bit-plane values. For instance, in a simple example, the bit-plane representing the LSBs of each pixel is displayed for 1 time slice, whereas the bit-plane representing the MSBs (most significant bits) may be displayed for 2n/2 time slices. Because a time slice is only 33.3/255 milliseconds long, the SLM must be capable of loading the LSB bit-plane within that time period. The time for loading the LSB bit-plane is the peak data rate.
A high peak data rate puts high throughput demands on the design of SLMs. To minimize the peak data rate, modifications to the above-described loading scheme have been devised. These loading schemes are acceptable only to the extent that they minimize visual artifacts in the displayed image.
One such modification uses an SLM whose pixel elements are grouped into reset groups that are separately loaded and addressed. This reduces the amount of data to be loaded during any one time, and permits the LSB data for each reset group to be displayed at a different time during the frame period. This configuration is described in U.S. Pat. No. 5,548,301, incorporated herein by reference.
Another method of PWM of frames of data used by a spatial light modulator having individually addressable pixel elements is described in U.S. Pat. No. 5,497,172, incorporated herein by reference. In that approach, the display period for each frame of data is divided into a number of time slices. Each frame of data is formatted into bit-planes, with each bit-plane having one bit of data for each pixel element and representing a bit-weight of the intensity value to be displayed by that pixel element. Each bit-plane has a display time corresponding to a number of time slices. The bit-planes are then sub-formatted into reset groups, each reset group having data for a group of pixel elements to be addressed at a different time from other pixel elements. The display times of reset groups from bit-planes of one or more of the more significant bit weights are segmented into two or more segments, which permits those display times to be distributed throughout the frame period. The loading of memory cells associated with the pixel elements is then performed in three phases. First, front-frame loading loads about half of the segments, such that, for all reset groups, segments having the same bit weight are loaded at substantially the same time. Then, mid-frame loading loads the reset groups of bit-planes of one or more of the less significant bits. Finally, end-frame loading loads the remaining segments, such that for all reset groups, segments having the same bit-weight are loaded at substantially the same time. This approach provides the advantage that it successfully implements data loading for split reset configurations. It provides good picture quality, both when the image is in motion and when it is still, by combining features of different data loading methods. The method does not require increased bandwidth or result in lower light efficiency, as compared to other split reset addressing methods.
An inherent problem with displays using Pulse Width Modulation (PWM) usually involves a tradeoff between brightness, color separation, PWM power consumption, and PWM temporal artifacts. Optimizing one of these parameters typically results in degradation in performance of the others.
It is well known that the power consumption attributed to the PWM sequence is linearly proportional to the number of bit splits in the sequence. For battery powered systems (e.g. handheld pico projectors), reducing the PWM power consumption can lead to longer “run” times between charges by decreasing the number of bit splits in the PWM sequences. This, however, introduces visible PWM artifacts using present day display methods.
Likewise, when the display time for a color is small relative to the system's load time, the likelihood of image quality artifacts is greatly increased. Such artifacts become easier to see with each successive generation of products as brightness improves.
Additionally, due to the processor-to-DMD bandwidth limitations of some systems, the amount of PWM bit splitting is limited by the hardware due to the excessive time it takes to load the DMD. For such systems (e.g. a pico projector embedded in a cell phone) a new technique must be found that addresses the poor PWM image quality resulting from reduced bit spitting.
All of the PWM temporal artifacts mentioned above are the result of large time separations between PWM bit planes. Decreasing the time separation between PWM bit planes of the same color leads to better PWM performance.
Additional background is disclosed in U.S. Pat. Nos. 6,115,083 and 6,201,521, the entireties of both of which are incorporated herein by reference.